Wednesday, June 18, 2025

Tiny gallium nitride transistors boost chip speed and efficiency in new 3D design | Phys.org

Tiny gallium nitride transistors boost chip speed and efficiency in new 3D design

Researchers have developed a new fabrication process that integrates high-performance gallium nitride transistors onto standard silicon CMOS chips in a way that is low-cost and scalable. Credit: Massachusetts Institute of Technology

The advanced semiconductor material gallium nitride will likely be key for the next generation of high-speed communication systems and the power electronics needed for state-of-the-art data centers.

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Unfortunately, the high cost of gallium nitride (GaN) and the specialization required to incorporate this into conventional electronics have limited its use in commercial applications.

Now, researchers from MIT and elsewhere have developed a new fabrication process that integrates high-performance GaN transistors onto standard silicon CMOS chips in a way that is low-cost and scalable, and compatible with existing semiconductor foundries.

Their method involves building many tiny transistors on the surface of a GaN chip, cutting out each individual transistor, and then bonding just the necessary number of transistors onto a using a low-temperature process that preserves the functionality of both materials.

The cost remains minimal since only a tiny amount of GaN material is added to the chip, but the resulting device can receive a significant performance boost from compact, high-speed transistors. In addition, by separating the GaN circuit into discrete transistors that can be spread over the silicon chip, the new technology is able to reduce the temperature of the overall system.

The researchers used this process to fabricate a , an essential component in mobile phones, that achieves higher signal strength and efficiencies than devices with silicon transistors. In a smartphone, this could improve call quality, boost wireless bandwidth, enhance connectivity, and extend battery life.

Because their method fits into standard procedures, it could improve electronics that exist today as well as future technologies. Down the road, the new integration scheme could even enable quantum applications, as GaN performs better than silicon at the cryogenic temperatures essential for many types of quantum computing.

"If we can bring the cost down, improve the scalability, and, at the same time, enhance the performance of the electronic device, it is a no-brainer that we should adopt this technology. We've combined the best of what exists in silicon with the best possible gallium nitride electronics.

"These hybrid chips can revolutionize many commercial markets," says Pradyot Yadav, an MIT graduate student and lead author of a paper on this method. 

The paper was presented at the RTu2C session of the Radio Frequency Integrated Circuits Symposium (RFIC 2025) held 15–17 June 2025 in San Francisco, CA.

"To address the slowdown of Moore's Law in transistor scaling, heterogeneous integration has emerged as a promising solution for continued system scaling, reduced form factor, improved power efficiency, and cost optimization.

"Particularly in wireless technology, the tight integration of compound semiconductors with silicon-based wafers is critical to realizing unified systems of front-end integrated circuits, baseband processors, accelerators, and memory for next-generation antennas-to-AI platforms.

"This work makes a significant advancement by demonstrating 3D integration of multiple GaN chips with silicon CMOS and pushes the boundaries of current technological capabilities," says Atom Watanabe, a research scientist at IBM who was not involved with this paper.

More information: 3D-Millimeter Wave Integrated Circuit (3D-mmWIC) : A Gold-Free 3D-Integration Platform for Scaled RF GaN-on-Si Dielets with Intel 16 Si CMOS. IEEE Radio-Frequency Integrated Circuit Symposium (RFIC), San Francisco, CA, Jun. 2025.

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